1. Field of the Invention
The present invention relates to a signal compensator circuit and a demodulator circuit which are applicable, for example, to a receiver for mobile communications.
2. Description of the Related Art
FSK (Frequency Shift Keying) signals often used in radio communications suffer from offset variations which may occur in a DC potential of a detected signal due to influences such as a difference between a received signal frequency and a predefined carrier frequency.
U.S. Pat. No. 6,104,238 (hereinafter called xe2x80x9creference 1xe2x80x9d) discloses a technique of suppressing variations in a DC potential of an output of a detector circuit, which involves smoothing the detected output, adding a DC component of the detected output to a frequency control signal for a channel selector filter or the like at the preceding stage, and changing the center frequency of the channel selector filter, in order to follow the variations in the DC offset.
U.S. Pat. No. 5,412,692 (hereinafter called xe2x80x9creference 2xe2x80x9d) in turn discloses that a maximum level and a minimum level of a detected output signal are detected, and an intermediate potential between the maximum and minimum levels is generated for use as a reference potential for a comparator to derive a final output signal. The intermediate potential follows variations in a DC potential of the detected output.
Some types of radio communication systems time-division-multiplexes a transmission state and a reception state. In addition, other than sequential switching between the transmission state and the reception state, a pause state (a state in which a supply voltage is applied, but neither transmission nor reception is performed) may exist in some cases during the switching. For this reason, at the time a communication apparatus switches to the reception state, a received signal suddenly reaches a receiver unit of the communication apparatus, thereby causing a sudden change in a DC potential of a detected signal at that time.
Generally, in a radio communication system, a preamble pattern is added to the beginning of a transmission signal thereof, and used to compensate for the above-mentioned sudden change in a DC potential.
However, the length of the preamble pattern differs from one radio communication system to another in particular applications. For reliably demodulating a signal with an extremely short length of pattern (for example, approximately four bits), it is necessary to rapidly follow the sudden change in the DC potential.
A transmission signal in turn may include a so-called same-code sequence pattern which is comprised of a sequence of high levels or a sequence of low levels. A demodulator circuit is required to operate until a sequence length defined for an applied system even for this same-code sequence pattern without signal errors. Generally, a tolerance to a signal error caused by the same-code sequence pattern (hereinafter simply called the xe2x80x9csame-code sequence tolerancexe2x80x9d) runs counter to the aforementioned operation involved in the rapid compensation for a sudden change in a DC potential.
In the circuit configuration described in reference 1, a time required for the DC potential compensation is the sum of a time required for smoothing a detected output and an absolute delay time inherent to a channel selector filter and a detector circuit. Therefore, a demodulator circuit which employs a high-order filter experiences difficulties in rapidly compensating for a DC potential since it requires a large delay time.
On the other hand, the circuit configuration described in reference 2 must reduce the time constant of an integrator circuit for detecting a maximum level and a minimum level of a detected output for realizing a rapid DC potential compensation, resulting in a deterioration in the same-code sequence tolerance.
It is therefore an object of the present invention to provide a signal compensator circuit which is capable of performing a rapid DC potential compensation and even capable of compensating for DC variations due to a same-code sequence pattern or the like, and a demodulator circuit including the signal compensator circuit.
To achieve the above object, a signal compensator circuit according to the present invention comprises variable gain amplifying means for amplifying an input signal with a gain variable with a gain control signal, first signal generating means for detecting variations in a DC level of an output signal from the amplifying means to generate a DC level variation signal indicative of the magnitude of the detected variations in the DC level, second signal generating means for detecting variations in an amplitude level of the output signal from the amplifying means to generate an amplitude level variation signal indicative of the magnitude of the detected variations in the amplitude level, and gain control signal generating means for integrating the DC level variation signal with predetermined time constant, integrating the amplitude level variation signal with a time constant smaller than the predetermined time constant, and generating the gain control signal based on results of the integrations.
Also, a demodulator circuit according to the present invention comprises detecting means for detecting a modulated input signal, variable gain amplifying means using an output from the detecting means as an input signal for amplifying the input signal with a gain variable with a gain control signal, first signal generating means for detecting variations in a DC level of an output signal from the amplifying means to generate a DC level variation signal indicative of the magnitude of the detected variations in the DC level, second signal generating means for detecting variations in an amplitude level of the output signal from the amplifying means to generate an amplitude level variation signal indicative of the magnitude of the detected variations in the amplitude level, gain control signal generating means for integrating the DC level variation signal with a predetermined time constant, integrating the amplitude level variation signal with a time constant smaller than the predetermined time constant, and generating the gain control signal based on results of the integrations, and comparing means for comparing the output signal from the amplifying means with a predetermined reference level to output a digital signal which has a definite logical level.